1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor device, and in particular to a technique for forming embedded wiring in a groove formed in an insulation layer.
2. Description of the Related Art
In recent years, semiconductor devices have been made finer and therefore delay caused by resistance in wirings and capacitance formed in the wirings has become relatively larger, such that it cannot be ignored in signal delay in the semiconductor devices. For this reason, copper that has smaller specific resistance compared to that of aluminum alloys has been considered as material for the wirings.
The copper wirings are formed in the following manner.
First, an insulation layer is formed on a semiconductor substrate. Grooves corresponding to the shape of the wirings are then formed in the insulation layer by a known photolithography technique. Then, an adhesion layer, for example, a titanium layer is formed all over the insulation layer. On the titanium layer is formed a titanium nitride layer as a diffusion protection layer. After the titanium nitride layer has been formed, a titanium layer is deposited by sputtering onto the titanium nitride layer and a thin layer of copper is then deposited by sputtering onto the deposited titanium layer. Next, the grooves are completely embedded by plating with copper, the copper layer that has been deposited by sputtering. The copper layer deposited by sputtering and the underlying titanium layer is then annealed to react with each other. Then, all the metal layers on the insulation layer are removed by a CMP (Chemical Mechanical Polishing) method, and thus metal portions serving as the wirings only remain in the grooves.
Therefore, it is an object of the present invention to provide a method for forming embedded wiring that can suppress reaction of the material of the wiring such as copper and material of an underlying metal layer such as titanium in an annealing process, and can suppress reduction in the cross-sectional size of the wiring. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to a first aspect of the present invention, a fabrication process for a semiconductor device, includes: forming an insulation layer on a substrate, forming a groove in the surface of the insulation layer, forming a diffusion protection layer on the surface of the insulation layer including inside of the groove, forming a reaction layer on the diffusion protection layer, forming an oxide layer on the surface of the reaction layer, forming a layer of a wiring material on the oxide layer to embed the groove, forming a layer of a mixture of the reaction layer, the layer of the wiring material and the oxide layer by annealing; and removing the diffusion protection layer, the mixture layer and the layer of the wiring material from the surface of the insulation layer except for the diffusion protection layer, the mixture layer and the layer of the wiring material in the groove.
In an embodiment of the present invention, the fabrication method further includes forming an adhesion layer for improving adhesion between the insulation layer and the diffusion protection layer. In this case, the diffusion protection layer is formed on the adhesion layer.
In another embodiment of the present invention, the formation of the layer of the wiring material includes: depositing a first wiring material on the oxide layer by sputtering, and forming a layer of a second wiring material on a layer of the first wiring material by plating.
In still another embodiment of the present invention, the reaction layer may be formed of at least one of Ti, Zr, Al, Mg, Si, Ag, Zn, Au, P, Sn, Be, Pd, In, Pt, Mn, Ga and Ge.
In still another embodiment of the present invention, the removal of the diffusion protection layer, the mixture layer and the layer of the wiring material except for the diffusion protection layer, the mixture layer and the layer of the wiring material in the groove is performed by chemical mechanical polishing.
In still another embodiment of the present invention the oxide layer is formed by exposing to the atmosphere, the substrate above which the reaction layer is formed.
In still another embodiment of the present invention, the oxide layer is formed by washing and scrubbing the reaction layer.
According to a second aspect of the present invention, a fabrication method for a semiconductor device includes: forming an insulation layer on a substrate, forming a groove in the surface of the insulation layer, forming a diffusion protection layer on the surface of the insulation layer including inside of the groove, forming an alloy layer containing a wiring material on the diffusion protection layer, forming a layer of the wiring material on the alloy layer to embed the groove, making the alloy layer and the layer of the wiring material react with each other by annealing; and removing the diffusion protection layer and the layer of the wiring material from the surface of the insulation layer except for the diffusion protection layer and the layer of the wiring material in the groove.
In an embodiment of the present invention, a thickness of the alloy layer is increased by the reaction of the alloy layer and the layer of the wiring material.
In another embodiment of the present invention, the alloy layer may contain two elements selected from the group consisting of the wiring material, Ti, Zr, Al, Mg, Si, Ag, Zn, Au, P, Sn, Be, Pd, In, Pt, Mn, Ga and Ge.
In still another embodiment of the present invention, the alloy layer may comprise two alloys, each of which two alloys contains three elements selected from the group consisting of the wiring material, Ti, Zr, Al, Mg, Si, Ag, Zn, Au, P, Sn, Be, Pd, In, Pt, Mn, Ga and Ge.
In still another embodiment of the present invention, the fabrication method further includes forming an oxide layer on the alloy layer, wherein the layer of the wiring material is formed on the oxide layer.
According to a third aspect of the present invention, a fabrication method for a semiconductor device includes: forming a layer of an organic low dielectric constant material on a substrate; forming a groove in the surface of the layer of the organic low dielectric constant material; forming a reaction layer on the surface of the layer of the organic low dielectric constant material including inside of the groove; forming an oxide layer on the surface of the reaction layer; forming a layer of a wiring material above the reaction layer on which the oxide layer has been formed so as to embed the groove; forming a layer of a mixture of the diffusion protection layer and the reaction layer by annealing; and removing the layer of the mixture and the layer of the wiring material away from the surface of the insulation layer except for the layer of the mixture and the layer of the wiring material in the groove.
According to a fourth aspect of the present invention, a fabrication method for a semiconductor device includes: forming a layer of an organic low dielectric constant material on a substrate; forming a groove in the surface of the layer of the organic low dielectric constant material; forming an alloy layer containing a wiring material on the layer of the organic low dielectric constant material including inside of the groove; forming a layer of the wiring material on the surface of the alloy layer to embed the groove; making the alloy layer and the layer of the wiring material react with each other by annealing; and removing the alloy layer and the layer of the wiring material on the surface of the insulation layer except for the alloy layer and the layer of the wiring material in the groove.
In an embodiment of the present invention, the fabrication method further includes forming an oxide layer on the alloy layer, wherein the layer of the wiring material is formed above the alloy layer on which the oxide layer has been formed.
According to a fifth aspect of the present invention, a fabrication method for a semiconductor device includes: forming an insulation layer on a substrate; forming a groove in the surface of the insulation layer; forming a titanium nitride layer that is stabilized on the surface of the insulation layer including inside of the groove; forming a coarse titanium nitride layer on the stabilized titanium nitride layer; oxidizing the surface of the coarse titanium nitride layer; forming a layer of a wiring material above the coarse titanium nitride layer on which an oxide layer has been formed so as to embed the groove; forming a layer of a mixture of the oxide layer and the layer of the wiring material by annealing; and removing the titanium nitride layer, the layer of the mixture and the layer of the wiring material from the surface of the insulation layer except for the titanium nitride layer, the layer of the mixture and the layer of the wiring material in the groove.
In an embodiment of the present invention, the stabilized titanium nitride layer is formed by repeating: deposition of a titanium nitride layer having a predetermined thickness by CVD and; a plasma treatment for the surface of the titanium nitride layer deposited by CVD, while the coarse titanium nitride layer is deposited by CVD.
In another embodiment of the present invention, the coarse titanium nitride layer is deposited by CVD using Tetra Di Methyl Amido Titanium as a material.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.